1. Field of the Invention
The present invention relates to an organic EL element drive circuit and an organic EL display device using the same and, in particular, the present invention relates to an improvement of an organic EL element drive circuit for a column line (one of anode side drive lines of an organic EL panel), with which, when the organic EL element drive circuit is formed as an IC, freedom of a wiring and a layout thereof is increased, an area of the organic EL element drive circuit can be reduced and power consumption thereof can be reduced, and an organic EL display device using the same organic EL element drive circuit.
2. Description of the Prior Art
It has been known that an organic EL display device, which realizes a high luminance display by spontaneous light emission, is suitable for a display on a small display screen and the organic EL display device has been attracting public attention as the next generation display device to be mounted on a portable telephone set, a PHS, a DVD player or a PDA (Personal Digital Assistants), etc. Known problems of the organic EL display device are that, when it is driven by voltage as in a liquid crystal display device, luminance variation thereof becomes substantial and that, since there is difference in sensitivity between R (red), G (green) and B (blue), a control of luminance of a color display becomes difficult. In view of these problems, an organic EL display device using current drive circuits has been proposed recently. For example, JPH10-112391A discloses a technique with which the luminance variation problem is solved by employing a current drive system.
An organic EL display panel of an organic EL display device for a portable telephone set, a PHS, etc., having 396 (=132×3) terminal pins for column lines and 162 terminal pins for row lines has been proposed. However, there is a tendency that the number of column lines as well as row lines is further increased.
An output stage of a current drive circuit of such organic EL display panel of either the active matrix type or the simple matrix type includes a current source drive circuit, such as an output circuit constructed with a current mirror circuit, for each of the terminal pins. A drive stage thereof includes a parallel-driven type current mirror circuit (reference circuit distribution circuit) having a plurality of output side transistors for each of the terminal pins as disclosed in JP2002-82662 (domestic priority application claiming priorities of JP2001-86967 and JP2001-396219) corresponding to U.S. patent application Ser. No. 10,102,671. In the disclosed drive stage, a plurality of mirror currents are generated correspondingly to the respective terminal pins by a reference current supplied from a reference current generator circuit to thereby drive the output circuits and by supplying them to the respective pins. Alternatively, the mirror currents supplied to the respective terminal pins are amplified by respective k-time current amplifier circuits, where k is an integer equal to or larger than 2, and the output circuits are driven with the amplified currents. The k-time amplifier circuit is disclosed in JP2002-33719, in which D/A converter circuits are provided correspondingly to the respective terminal pins and the D/A converter circuit converts display data corresponding to the column side terminal pins into analog data to generate column side drive currents simultaneously.
In this disclosed circuit construction, a peak current is generated for initially charging an organic EL element having capacitive load characteristics to drive the organic EL element. The peak current may be generated in a circuit portion preceding to the drive stage as a reference current, in a circuit portion succeeding to a D/A converter circuit as disclosed in JP2002-33719 or in a current output stage.
FIG. 3 shows a technique disclosed in U.S. patent application Ser. No. 10,360,715 corresponding to JP2002-33937 and assigned to the present assignee, in which a peak current generator circuit is provided in a D/A converter circuit.
In FIG. 3, a column driver of an organic EL element drive circuit includes a drive current generator circuit 10 for generating a drive current corresponding to a display data, a D/A converter circuit 11 provided in the drive current generator circuit 10, a constant current source 12 for supplying a current having value Ip, a current mirror type current output circuit 13, a peak current generator circuit 14, a control circuit 15 and a register 16.
The D/A converter circuit 11 includes an N channel input side transistor TNa and an N channel input side transistor TNp mirror-connected to the N channel input side transistor TNa. The D/A converter circuit 11 further includes N channel output side transistors TNb to TNn−1, which are current-mirror connected to the input side transistors TNa and TNp.
Channel width (gate width) ratio of the transistors TNa to TNb is set to 1:9. A source of the transistor TNa is grounded through a resistor Ra and a source of the transistor TNp is grounded through a resistor Rpa and a switch circuit SWpa. For the sake of simplicity of description, a switch SWa provided between the resistor Ra and ground GND, which is shown in FIG. 1 of U.S. patent application Ser. No. 10,360,715, is not shown in FIG. 3.
The channel width (gate width) ratio of 1:9 may be obtained by parallel-connecting 9 of 10 MOS transistors having identical configurations and good pairing characteristics to the remaining one MOS transistor.
The input side transistors TNa and TNp are connected to an input terminal 11a and supplied with the current Ip from the constant current source 12 through the input terminal 11a. 
When the current having the value Ip flows in the input side transistor TNa as an operating current, a peak current Ia (=Ipa) corresponding to a display data is generated at an output terminal lib of the D/A converter circuit 11. When the current Ip is branched and flows in the input side transistors TNa and TNp, an input side drive current of the current mirror circuit becomes substantially one-tenth the current Ip and a drive current Ia (=Ipa/10) corresponding to the display data is generated at the output terminal 11b of the D/A converter circuit 11.
Resistors Rb to Rn−1 are provided between sources of the output side transistors TNb to TNn−1 and drains of transistors Trb to Trn−1, respectively. With these resistors, it is possible to improve preciseness of the current pairing characteristics of the D/A converter circuit 11.
Gates of the transistors Trb to Trn−1 are connected to input terminals Do to Dn−1 to which n-bit display data are inputted. Thus, the transistors Trb to Trn−1 are supplied with the display data from the register 16. Sources of the transistors Trb to Trn−1 are grounded.
The current mirror type current output circuit 13 includes a drive level shifter circuit 13a and an output stage current mirror circuit 13b. 
The drive level shifter circuit 13a functions to transmit the output of the D/A converter circuit 11 to the output stage current mirror circuit 13b and includes an N channel MOS FET TNv. A gate of the transistor TNv is connected to a bias line Vb and a source of the same transistor is connected to the output terminal 11b of the D/A converter circuit 11. A drain of the transistor TNv is connected to an input terminal 13c of the output stage current mirror circuit 13b. 
Therefore, assuming that the output current of the D/A converter circuit 11 is Ia, it is possible to generate a drive current of Ia at the input terminal 13c. 
The output stage current mirror circuit 13b includes a current mirror circuit composed of P channel MOS FETs TPu and TPw for correcting a gate drive voltage and P channel MOS FETs TPx and TPy, which are driven by the transistors TPu and TPw. Gate width ratio of the transistor TPx to the transistor TPy of the output stage current mirror circuit 13b is 1:N. Sources of the transistors TPx and TPy are connected to not a power source line +VDD but a power source line +Vcc which is higher than +VDD, for example, about +15V. The transistor TPy is connected to a column side terminal pin 9 and drives the terminal pin 9 by supplying drive current N Ia. An organic El element 8 is connected between the terminal pin 9 and ground GND. Incidentally, Vc in FIG. 3 is also a bias line.
The input side transistor TNp, the resistor Rpa and the switch circuit SWpa constitute the peak current generator circuit 14 and the switch circuit SWpa is turned OFF for a constant time period tp in an initial stage of driving without a control signal CONT from the control circuit 15 and is turned ON by the control signal CONT after the time period tp lapses.
Since the switch circuit SWpa does not receive the control signal CONT from the control circuit 15 in the initial driving stage, the current Ip flows in the input side transistor TNa. Therefore, a current, which is several times, for example, M times, the current Ip, corresponding to the display data set in the respective input terminals D0 to Dn−1, that is, M×Ip (=Ipa), is generated, so that the peak current Ia=M×Ip is generated at the output terminal 11b of the D/A converter circuit 11. The control signal CONT is generated after the peak current generating period tp and the switch circuit SWpa is turned ON. The current in the input side transistor TNa is branched to the input side transistor TNp. Therefore, a drive current, which is Ip/10, flows in the input side transistor TNa and a drive current 9×Ip/10 flows in the input side transistor TNp according to the gate width ratio 1:9 of these transistors. As a result, the input side drive current of the current mirror circuit becomes substantially 1/10 and the current Ia(=Ipa/10) is generated at the output terminal 11b of the D/A converter circuit 11.
There is a recent tendency that the number of drive pins is increasing due to request of high resolution. Correspondingly to the increase of the drive terminal pins, the number of the output stages of the current drive circuit tends to be increased. Therefore, power consumption is increased correspondingly, so that a reduction of power of the current drive circuit becomes necessary. In order to solve this problem, the current drive circuit constructed with MOS transistors, such as shown in FIG. 3, has been proposed. In such output stage constructed with these MOS transistors (current mirror type current output circuit 13), the drive circuit composed of the MOS transistors and the current mirror output circuit composed of the MOS transistors and connected in series with the drive circuit are connected to the higher voltage power source line.
When the current drive circuit composed of the MOS transistors is used, various currents for operating the circuit, such as bias currents and currents required to correct the base current, etc., are necessary as in the case where a current drive circuit composed of bipolar transistors and a leak current problem occurs. These currents are increased with increase of the number of terminal pins and an influence of these currents on power consumption of the whole circuit becomes large correspondingly, resulting in an obstacle in reducing the power consumption.
Further, in the current drive circuit shown in FIG. 3, the circuit constructions of the D/A converter circuit 11, the peak current generator circuit provided in the D/A converter circuit 11 and the output stage composed of the MOS transistors are different. Such current drive circuit must be designed by determining layouts and wiring of the respective circuits. Therefore, the efficiency of layout is low and the freedom of wiring is low. For this reason, it becomes relatively difficult to reduce the size of circuit.